Dynamic random access memories (DRAMs) utilize a plurality of memory cells arranged in an array of rows and columns. Each of the memory cells is comprised of a single MOS transistor and a memory cell capacitor. The array is accessed such that selection of any given memory cell requires selection of an entire row of memory cells, with the data therein read out to the associated data line. Thereafter, column decode circuitry will determine which data lines are output from the memory.
In order to access an entire row of memory cells, a word line is provided that is disposed parallel to a given row of memory cells, which word line is raised from a low voltage to a high voltage during the Read operation. For large memory arrays, the conventional technique is to utilize a polycrystalline silicon gate electrode and arrange a transistor such that the layer that forms the gate electrodes is also the layer that forms the word line, wherein a single conductive strip can be disposed on a given row, where it overlies the gate oxide to form a gate electrode. This gate electrode is typically patterned and etched from a single layer of polycrystalline silicon (poly).
As memory arrays increase in size above the 256 Meg DRAM products, the transistors become smaller and the word lines become narrower. This has the result that the overall impedance of the word line will increase. Although the dopant level in the poly word line can be increased to vary the conductance thereof, typically the dopant level proximate to the gate oxide overlying the channel region of the transistor is controlled to achieve an optimum transistor. It is then necessary to accept the conductivity of the material that forms the transistor gate electrode as the word line. However, in order to improve the propagation delay along the word line, a lower conductivity material has been developed that is formed of a refractory metal silicide layer, such as titanium disilicide or tungsten silicide. The refractory metal silicides are formed by first depositing a thin layer of refractory metal over the polysilicon and then annealing the substrate at a temperature typically above 600.degree. C. This results in the consumption of the polysilicon and the refractory metal to form the refractory metal silicide. This typically only consumes a portion of the upper layer, such that the lower portion of the polysilicon remains intact proximate to the gate oxide, such that the characteristics of the transistor are unchanged, while the overall conductivity of the word line is increased. However, one disadvantage to the formation of these refractory metal silicide layers is the additional process steps that are required.